Cover

Contents

Figures

1.1 Address Map

1.2 vRAM Organization

2 Horizontal - LCA

2.1 Block Diagram

2.2 Data Bus

2.3 Address Decode

2.4 Dot Clock

2.5 Horizontal Counter

2.6 Horizontal Maximum

2.7 Horizontal Sync Start

2.8 Horizontal Sync End

2.9 Video Output

2.10 Output Port

2.1 Constraints File

2.2 Wolrd View

3 Vertical - LCA

3.1 Block Diagram

3.2 vRAM Timing

3.3 DMA Timing

3.4 Vertical Counter

3.5 Address Generator

3.6 Address Multiplexer

3.7 Keyboard

3.8 Date Bus

3.9 Sync Register

3.10 Interrupts

3.1 Constraints File

3.2 World View